Abstract Ferroelectric hafnium zirconium oxide can increase charge density in scaled capacitors, but its high coercive field limits the low-voltage, high endurance switching required for dynamic random-access memory and embedded ferroelectric memories. Here we show that plasma-engineered (111)-textured TiN electrodes with N-rich, oxidation-resistant surfaces suppress interfacial oxidation and enable robust switching in 5 nm Hf 0.5 Zr 0.5 O 2 capacitors. The devices exhibit saturated hysteresis at 0.6 V, with 2 P r = 31.5 μC cm −2 and E c = 0.62 MV cm −1 , and no hard electrical breakdown through 10 12 bipolar cycles. Their nucleation-limited switching kinetics extrapolate to sub-nanosecond polarisation reversal at DRAM-relevant capacitor areas. At 1.1 V, circuit simulations of a common plate 1T–1 C cell yield short- and long-term stand-by sensing margins of 482 and 201 mV under a 20 fF bit line load. Electrode texture and interface engineering therefore enable low-voltage, high speed switching without compromising endurance, mitigating the practical Kay–Dunn scaling penalty and the speed–endurance dilemma.